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Wireless Components
434 MHz ASK/FSK Transmitter in 10-pin Package TDK 5100 F Version 0.1
Target Specification July 2003 Confidential
Preliminary
Confidential Revision History Current Version: Version 0.1 as of July 2003 Previous Version: Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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TDK 5100 F
Preliminary
Product Info
Product Info
General Description The TDK 5100 F is a single chip ASK/ Package FSK transmitter for the frequency band 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features are a power down mode and a divided clock output.
Features
I I I I I I
fully integrated frequency synthesizer VCO without external components ASK and FSK modulation frequency range 433-435 MHz high efficiency power amplifier (typically 5 dBm) low supply current (typically 7mA)
I I I I I I I
voltage supply range 2.1 - 4 V temperature range - ... +125C 40 power down mode crystal oscillator 13.56 MHz FSK-switch divided clock output for C low external component count
Applications
I I I
Tire pressure monitoring systems Keyless entry systems Remote control systems
I I
Alarm systems Communication systems
Ordering Information
Type TDK 5100 F available on tape and reel Ordering Code Package P-TSSOP-10
t.b.d.
Wireless Components
Product Info
Target Specification, July 2003
1
Product Description
Contents of this Chapter 1.1 1.2 1.3 1.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
TDK 5100 F
Preliminary
Product Description
1.1 Overview
The TDK 5100 F is a single chip ASK/FSK transmitter for the frequency band 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features are a power down mode and a divided clock output. The IC can be used for both ASK and FSK modulation.
1.2 Applications
I I I I I
Tire pressure monitoring systems Keyless entry systems Remote control systems Alarm systems Communication systems
1.3 Features
I I I I I I I I I I I I I
fully integrated frequency synthesizer VCO without external components ASK and FSK modulation switchable frequency range 433-435 MHz high efficiency power amplifier (typically 5 dBm) low supply current (typically 7 mA) voltage supply range 2.1 - 4 V temperature range - 40C ... 125C power down mode crystal oscillator 13.56 MHz FSK-switch divided clock output for C low external component count
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1-2
Target Specification, July 2003
TDK 5100 F
Preliminary
Product Description
1.4 Package Outlines
1.1 max.
0.15 max.
H
A 0.22 0.05 0.08
M
0.1 A ABC
0.09
0.5
0.42 +0.15 -0.1 4.9 0.25
M
6 max.
3 0.1
C
+0.08 0.125 -0.05
0.85 0.1
ABC
3 0.1 Index Marking
B
Figure 1-1
P-TSSOP-10
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2
Functional Description
Contents of this Chapter 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Recommended Timing Diagrams for ASK- and FSK-Modulation . 2-10
TDK 5100 F
Preliminary
Functional Description
2.1 Pin Configuration
CLKOUT
1
10
PDWN
VS
2
9
PAOUT
GND
3
TDK 5100F
8
PAGND
FSKOUT
4
7
FSKDTA
COSC
5
6
ASKDTA
Pin_config.wmf
Figure 2-1 Table 2-1
IC Pin Configuration
Pin No. 1 2 3 4 5 6 7 8 9 10
Symbol CLKOUT VS GND FSKOUT COSC ASKDTA FSKDTA PAGND PAOUT PDWN
Function Clock Driver Output (847.5 kHz) Voltage Supply Ground Frequency Shift Keying Switch Output Crystal Oscillator Input (13.56 MHz) Amplitude Shift Keying Data Input Frequency Shift Keying Data Input Power Amplifier Ground Power Amplifier Output (434 MHz) Power Down Mode Control
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2-2
Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
2.2 Pin Definitions and Functions
Table 2-2
Pin No.
1
Symbol
CLKOUT
Interface Schematic1)
Function
Clock output to supply an external device. An external pull-up resistor has to be added in accordance to the driving requirements of the external device. The clock frequency is 847.5 kHz.
VS 1 300
2
VS
This pin is the positive supply of the transmitter electronics. An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 3) as short as possible. General ground connection.
VS VS
3 4
GND FSKOUT
This pin is connected to a switch to GND (pin 3). The switch is closed when the signal at FSKDTA (pin 7) is in a logic low state.
200 A 1.5 k 4
The switch is open when the signal at FSKDTA (pin 7) is in a logic high state. FSKOUT can switch an additional capacitor to the reference crystal network to pull the crystal frequency by an amount resulting in the desired FSK frequency shift of the transmitter output frequency. This pin is connected to the reference oscillator circuit. The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin.
5
5
COSC
VS VS
6 k
100 A
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Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
6
ASKDTA
VS + 1.2 V
Digital amplitude modulation can be imparted to the Power Amplifier through this pin. A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier. A logic low (ASKDTA < 0.5 V) disables the Power Amplifier.
60 k 6 + 1.1 90 k 5 0 pF 30 A
7
FSKDTA
VS + 1.2 V
60 k 7 + 1.1 V 90 k 3 0 A
Digital frequency modulation can be imparted to the Xtal Oscillator by this pin. The VCO-frequency varies in accordance to the frequency of the reference oscillator. A logic high (FSKDTA > 1.5V or open) sets the FSK switch to a high impedance state. A logic low (FSKDTA < 0.5 V) closes the FSK switch from FSKOUT (pin 4) to GND (pin 3). A capacitor can be switched to the reference crystal network this way. The Xtal Oscillator frequency will be shifted giving the designed FSK frequency deviation. Ground connection of the power amplifier. The RF ground return path of the power amplifier output PAOUT (pin 9) has to be concentrated to this pin. RF output pin of the transmitter. A DC path to the positive supply VS has to be supplied by the antenna matching network. Disable pin for the complete transmitter circuit.
8
PAGND
9
9
PAOUT
8
10
PDWN
VS 40 A (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns off all transmitter functions. A logic high (PDWN > 1.5 V) gives access to all transmitter functions. PDWN input will be pulled up by 40 A internally by either setting FSKDTA or ASKDTA to a logic high-state.
5 k 10 "ON" 150 k
250 k
1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode.
In Power Down Mode, the values are zero or high-ohmic.
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Wireless Components
FSK Data Input ASK Data Input Power Down Control Power Supply VS
Figure 2-2
7 6 10 2
OR
2.3 Functional Block diagram
Functional Block diagram
2-5
4
On Pow er Supply
FSK Switch
Crystal 13.56 M Hz
5
XTA L Os c PFD :64 V CO :2
Pow er A MP
9
Power Amplifier Output
8
:16 LF
Power Amplifier Ground
1
Clock Output
3
Ground
Preliminary
Target Specification, July 2003
TDK 5100 F
Functional Description
Blockdiagram.wmf
TDK 5100 F
Preliminary
Functional Description
2.4 Functional Blocks
2.4.1 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 868 MHz. The oscillator signal is fed both, to the synthesizer divider chain and to the power amplifier. The overall division ratio of the asynchronous divider chain is 64. The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip.
2.4.2 Crystal Oscillator
The crystal oscillator operates at 13.56 MHz.
The crystal frequency is divided by 16. The resulting 847.5 kHz are available at the clock output CLKOUT (pin1) to drive the clock input of a micro controller.
To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount by switching an external capacitor via FSKOUT (pin 4). The condition of the switch is controlled by the signal at FSKDTA (pin 7).
Table 2-3
FSKDTA (pin7) Low 1) Open2), High3) 1) Low: Voltage at pin < 0.5 V 2) Open: Pin open 3) High: Voltage at pin > 1.5 V
FSK Switch CLOSED OPEN
Wireless Components
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Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
2.4.3 Power Amplifier
The VCO frequency is divided by 2 and fed to the Power Amplifier. The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6).
Table 2-4
ASKDTA (pin 6) Low 1) Open2), High3)
1) Low: 2) Open: 3) High: Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V
Power Amplifier OFF ON
The Power Amplifier has an Open Collector output at PAOUT (pin 9) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 9) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 8) in order to reduce the amount of coupling to the other circuits.
2.4.4 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE MODE and the TRANSMIT MODE.
2.4.4.1 Power Down Mode
In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.3 nA at 3 V 25C. This current doubles every 8C. The values for higher temperatures are typically 14 nA at 85C and typically 600 nA at 125C.
2.4.4.2 PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is less than 1 msec when the specified crystal is used. The current consumption is typically 3.5 mA.
Wireless Components
2-7
Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
2.4.4.3 Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 7 mA when using a proper transforming network at PAOUT, see Figure 3-1.
2.4.4.4 Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin10). When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up internally. Forcing the voltage at the pins low overrides the internally set state. Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open.
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Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
The principle schematic of the power mode control circuitry is shown in Figure 2-5 .
PDW N A SKDTA FSKDTA
On
OR
Bias Sourc e 120 k Bias Voltage
120 k
On
FSK 434 MHz PA IC
FSKOUT PA OUT
PLL
Power_Mode.wmf
Figure 2-5
Power mode control circuitry
Table 2-5 provides a listing of how to get into the different power modes
Table 2-5
PDWN
Low1) Open2) High3) Open High Open Open 1) Low: 2) Open: 3) High:
FSKDTA
Low, Open Low Low, Open, High High Low, Open, High High Low, Open, High
ASKDTA
Low, Open Low Low
MODE
POWER DOWN
PLL ENABLE Low Open, High Open, High High TRANSMIT
Voltage at pin < 0.7 V (PDWN) Voltage at pin < 0.5 V (FSKDTA, ASKDTA) Pin open Voltage at pin > 1.5 V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not recommended.
Wireless Components
2-9
Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
2.4.5 Recommended Timing Diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
M o de s:
P ow er D o w n
P L L E na ble
T ran sm it
H igh
FSK DTA
Lo w
to t
DATA O p en , H igh
A SK DTA
Lo w
to t
m in. 1 m sec.
ASK_mod.wmf
Figure 2-6
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected
M o de s:
P ow er D o w n
P L L E na ble
T ran sm it
DATA H igh
FSK DTA
Lo w
to t
H igh
A SK DTA
Lo w
to t
m in. 1 m sec.
FSK_mod.wmf
Figure 2-7
FSK Modulation
Wireless Components
2 - 10
Target Specification, July 2003
TDK 5100 F
Preliminary
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
M o de s:
P ow er D ow n
P LL E na ble
Tran sm it
H igh
P DW N
Lo w
to t
D AT A O p en , H igh
A SK DTA
Lo w
to t
m in . 1 m se c.
Alt_ASK_mod.wmf
Figure 2-8
Alternative ASK Modulation
Alternative FSK Modulation
M o de s:
P ow er D o w n
P L L E na ble
T ran sm it
H igh
PDW N
Lo w
to t
O p en , H igh
A SK D TA
Lo w
to t
DATA O p en , H igh
FSK D TA
Lo w
to t
m in. 1 m sec.
Alt_FSK_mod.wmf
Figure 2-9
Alternative FSK Modulation
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TDK 5100 F
Preliminary
Functional Description
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2 - 12
Target Specification, July 2003
3
Applications
Contents of this Chapter
3.1 3.2 3.3 3.4 3.5 3.6 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 3-2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 3-4 Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 3-5 Design Hints on the Clock Output (CLKOUT). . . . . . . . . . . . . . . . . . . 3-7 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . 3-8
TDK 5100 F
Preliminary
Applications
3.1 50 Ohm-Output Testboard Schematic
T.b.d.
50ohm_test.wmf
Figure 3-1
50-output testboard schematic
Wireless Components
3-2
Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
3.2 50 Ohm-Output Testboard Layout
T. .b.d
Figure 3-2
Top Side of TDK 5100 F-Testboard with 50 -Output
T. .b.d
Figure 3-3
Bottom Side of TDK 5100 F-Testboard with 50 -Output
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TDK 5100 F
Preliminary
Applications
3.3 Bill of material (50 Ohm-Output Testboard)
The bill of materials is to be determined.
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3-4
Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
3.4 Application Hints on the Crystal Oscillator
1. Application Hints on the crystal oscillator
The crystal oscillator achieves a turn on time less than 1 msec when the specified crystal is used. To achieve this, a NIC oscillator type is implemented in the TDK 5100 F. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv.
-R
L
f, C L
Cv
IC
Cv =
1 1 + 2L CL
Formula 1)
CL: : L:
crystal load capacitance for nominal frequency angular frequency inductance of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced by a short to ground. Assume a crystal frequency of 13.56 MHz and a crystal load capacitance of CL = 20 pF. The inductance L at 13.5 MHz is about 4.6 H. Therefore C6 is calculated to 12 pF.
Cv =
1 1 + 2L CL
= C6
Wireless Components
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Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as shown below.
FS KD TA
FS KO U T
C sw -R L
COSC
f, C L C v1
C v2
IC
The frequency deviation of the crystal oscillator is multiplied with the divider factor N of the Phase Locked Loop to the output of the power amplifier. In case of small frequency deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated with the formula below.
CL =
CL m C 0
f 2(C 0 + CL ) (1 + ) N * f1 C1 2(C 0 + CL) f 1 (1 + ) N * f1 C1
CL: C0: f: : N: df:
crystal load capacitance for nominal frequency shunt capacitance of the crystal frequency = 2f: angular frequency division ratio of the PLL peak frequency deviation
Because of the inductive part of the TDK 5100 F, these values must be corrected by Formula 1. The value of Cv can be calculated.
Cv =
1 1 + 2L CL
Wireless Components
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Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram). If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Cv 2 = C 7 =
Csw Cv1 - (Cv +) (Cv1 + Csw) (Cv +) - Cv1
Csw:
parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
Remark:
These calculations are only approximations. The necessary values depend on the layout also and must be adapted for the specific application board.
3.5 Design Hints on the Clock Output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the microcontroller). RL can be calculated to:
RL =
1 fCLKOUT * 8 * CLD
Table 3-1 fCLKOUT=847 kHz CL[ pF] 5 10 20 RL[ kOhm] 27 12 6.8
Remark:
To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen.
Even harmonics of the signal at CLKOUT can interact with the crystal oscillator input COSC preventing the start-up of oscillation. Care must be taken in layout by sufficient separation of the signal lines to ensure sufficiently small coupling.
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Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
3.6 Application Hints on the Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of <<. A frequency selective network at the amplifier output passes the fundamental frequency component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collector of the power amplifier can be generalized by the equivalent circuit of Figure 3-4. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter.
VS L C RL
Equivalent_power_wmf.
Figure 3-4
Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for "critical" operation under idealized conditions at resonance is:
R LC =
V S2 2 * PO
The theoretical value of RLC for an RF output power of Po= 5 dBm (3.16 mW) is:
R LC
32 = = 1423 2 * 0 .00316
"Critical" operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high degree of efficiency under "critical" operating conditions can be explained by the low power losses at the transistor. During the conducting phase of the transistor, its collector voltage is very small. This way the power loss of the transistor, equal to iC*uCE , is minimized. This is particularly true for small current flow angles of <<. In practice the RF-saturation voltage of the PA transistor and other parasitics reduce the "critical" RLC.
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Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
The output power Po is reduced by operating in an "overcritical" mode characterised by RL > R LC. The power efficiency (and the bandwidth) increase when operating at a slightly higher RL, as shown in Figure 3-5. The collector efficiency E is defined as
E=
PO VS I C
The diagram of Figure 3-5 was measured directly at the PA-output at VS = 3 V. Losses in the matching circuitry decrease the output power by about 1.5 dB. As can be seen from the diagram, 550 is the optimum impedance for operation at 3 V. For an approximation of ROPT and POUT at other supply voltages those two formulas can be used:
ROPT ~ VS
and
POUT ~ ROPT
1 0 *E P o [m W ] 7 6 5 4 3 2 1 0 0 1000 2 000 30 00 R L [O h m ]
Power_output.wmf
1 0 *E Po
Figure 3-5
Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of "overcritical" operation. The depth of this dip will increase with higher values of RL.
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Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
As Figure 3-6 shows, detuning beyond the bandwidth of the matching circuit results in an increase of the collector current of the power amplifier and in some loss of output power. This diagram shows the data for the circuit of the test board at the frequency of 434 MHz. The effective load resistance of this circuit is RL = 550 , which is the optimum impedance for operation at 3 V. This will lead to a dip of the collector current of approx. 40%.
T.b.d.
tbd.wmf
Figure 3-6
Output power and collector current vs. frequency
C3, L2-C2 and C8 are the main matching components which are used to transform the 50 load at the SMA-RF-connector to a higher impedance at the PA-output (700 @ 3 V). L1 can be used for some finetuning of the resonant frequency but should not become too small in order to keep its losses low. The transformed impedance of 550+j0 at the PA-output-pin can be verified with a network analyzer using the following measurement procedure: 1. Calibrate your network analyzer. 2. Connect some short, low-loss 50 cable to your network analyzer with an open end on one side. Semirigid cable works best. 3. Use the Port Extension" feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable. 4. Connect the center-conductor of the cable to the solder pad of the pin PA" of the IC. The outer conductor has to be grounded. Very short connections have to be used. Do not remove the IC or any part of the matching-components! 5. Screw a 50 dummy-load on the RF-I/O-SMA-connector 6. Be sure that your network analyzer is AC-coupled and turn on the power supply of the IC. The TDK 5100 F must not be in Transmit-Mode. 7. Measure the S-parameter S11
Wireless Components
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Target Specification, July 2003
TDK 5100 F
Preliminary
Applications
T.b.d.
tbd.wmf
Figure 3-7
S-parameters of the load at the PA-output
Above you can see the measurement of the evalboard with a span of 100 MHz. The evalboard has been optimized for 3 V. The load is about 550+j0 at the transmit frequency. A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances of matching components. Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. The total spectrum of a typical 50 -Output testboard can be summarized as:
Table 3-2 Frequency Fundamental Fund -13.56 MHz Fund + 13.56 MHz Output Power 434 MHz Testboard +5 dBm t.b.d. t.b.d. t.b.d. t.b.d.
2nd harmonic 3rd harmonic
Wireless Components
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Target Specification, July 2003
1
Reference
Contents of this Chapter
1.1 1.2 1.3 1.3.1 1.3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 AC/DC Characteristics at 3V, 25C . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 AC/DC Characteristics at 2.1 V ... 4.0 V, -40C ... +125C. . . . . . . . . 1-5
TDK 5100 F
Preliminary
Reference
1.1 Absolute Maximum Ratings
The AC / DC characteristic limits are not guaranteed. The maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result.
Table 1-1 Parameter Symbol Limit Values Min Max - 40 - 40 Unit Remarks
Junction Temperature Storage Temperature Thermal Resistance Supply voltage Voltage at any pin excluding pin 9 Voltage at pin 9 Current into pin 4 ESD integrity, all pins ESD integrity, all pins excluding pin 9
TJ Ts RthJA VS Vpins Vpin9 Ipin4 VESD VESD
+150 +125 t.b.d.
C C K/W V V V mA kV kV JEDEC Standard JESD22-A114-B JEDEC Standard JESD22-A114-B No ESD-Diode to VS
- 0.3
+4.0 VS + 0.3 2 * VS 10 +1 +2
-0.3 -0.3 -10 -1 -2
Ambient Temperature under bias: TA = - 40C to +125 C Note: All voltages referred to ground (pins) unless stated otherwise. Pins 3 and 8 are grounded.
1.2 Operating Range
Within the operational range the IC operates as described in the circuit description.
Table 1-2 Parameter Symbol Limit Values Min Max Unit Test Conditions
Supply voltage Ambient temperature
VS TA
2.1 -40
4.0 125
V C
Wireless Components
1-2
Target Specification, July 2003
TDK 5100 F
Preliminary
Reference
1.3 AC/DC Characteristics
1.3.1
AC/DC Characteristics at 3V, 25C
Table 1-3 Supply Voltage V S = 3 V, Ambient temperature Tamb = 25 C Parameter Symbol Min Current consumption Limit Values Typ Max Unit Test Conditions
Power Down mode PLL Enable mode Transmit mode 434 MHz
Output frequency
IS PDWN IS PLL_EN IS TRANSM
0.3 3.5 7
100 4.2
nA mA mA
V (Pins 10, 6 and 7) < 0.2 V
Output frequency
Clock Driver Output (Pin 1)
fOUT
434
MHz
fOUT = 32 * fCOSC
Output current (High) Saturation Voltage (Low)1)
FSK Switch Output (Pin 4)
ICLKOUT VSATL
5 0.56
A V
VCLKOUT = VS ICLKOUT = 1 mA
On resistance On capacitance Off resistance Off capacitance
Crystal Oscillator Input (Pin 5)
RFSKOUT CFSKOUT RFSKOUT CFSKOUT 10
250 6
VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS
pF k
1.5
pF
Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin
CCOSCmax
5 100 4.6
pF
f = 13.56 MHz f = 13.56 MHz
H
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled ASK Transmit enabled Input bias current ASKDTA Input bias current ASKDTA ASK data rate
VASKDTA VASKDTA IASKDTA IASKDTA fASKDTA
0 1.5
0.5 VS 30
V V A A VASKDTA = VS VASKDTA = 0 V
-20 20
kHz
Wireless Components
1-3
Target Specification, July 2003
TDK 5100 F
Preliminary
Reference
Table 1-3 Supply Voltage V S = 3 V, Ambient temperature Tamb = 25 C Parameter Symbol Min FSK Modulation Data Input (Pin 7) Limit Values Typ Max Unit Test Conditions
FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate
VFSKDTA VFSKDTA IFSKDTA IFSKDTA fFSKDTA
0 1.5
0.5 VS 30
V V A A VFSKDTA = VS VFSKDTA = 0 V
-20 20
kHz
Power Amplifier Output (Pin 9)
Output Power2) at 434 MHz transformed to 50 Ohm
POUT434
5
dBm
Power Down Mode Control (Pin 10)
Power Down mode PLL Enable mode Transmit mode Input bias current PDWN
V PDWN V PDWN V PDWN IPDWN
0 1.5 1.5
0.7 VS VS 30
V V V A
VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = V S
1) 2)
Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA Power amplifier in overcritical C-operation Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency. Tolerances of the passive elements not taken into account.
Wireless Components
1-4
Target Specification, July 2003
TDK 5100 F
Preliminary
Reference
1.3.2
AC/DC Characteristics at 2.1 V ... 4.0 V, -40C ... +125C
Table 1-4 Supply Voltage V S = 2.1 V ... 4.0 V, Ambient temperature T amb = -40 C ... +125 C Parameter Symbol Min Current consumption Limit Values Typ Max A Unit Test Conditions
Power Down mode PLL Enable mode Transmit mode
Output frequency
IS PDWN IS PLL_EN IS TRANSM 3.5 7
4 4.6
V (Pins 10, 6 and 7) < 0.2 V
mA mA
Output frequency1)
Clock Driver Output (Pin 1)
fOUT
434
MHz
fOUT = 32 * fCOSC
Output current (High) Saturation Voltage (Low)2)
FSK Switch Output (Pin 4)
ICLKOUT VSATL
5 0.5
A V
VCLKOUT = VS ICLKOUT = 0.6 mA
On resistance On capacitance Off resistance Off capacitance
Crystal Oscillator Input (Pin 5)
RFSKOUT CFSKOUT RFSKOUT CFSKOUT 10
280 6
VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS
pF k
1.5
pF
Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin
CCOSCmax
5 100 4.6
pF
f = 13.56 MHz f = 13.56 MHz
H
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled ASK Transmit enabled Input bias current ASKDTA Input bias current ASKDTA ASK data rate
VASKDTA VASKDTA IASKDTA IASKDTA fASKDTA
0 1.5
0.5 VS 33
V V A A VASKDTA = VS VASKDTA = 0 V
-20 20
kHz
Wireless Components
1-5
Target Specification, July 2003
TDK 5100 F
Preliminary
Reference
Table 1-4 Supply Voltage V S = 2.1 V ... 4.0 V, Ambient temperature T amb = -40 C ... +125 C Parameter Symbol Min FSK Modulation Data Input (Pin 7) Limit Values Typ Max Unit Test Conditions
FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate
VFSKDTA VFSKDTA IFSKDTA IFSKDTA fFSKDTA
0 1.5
0.5 VS 33
V V A A VFSKDTA = VS VFSKDTA = 0 V
-20 20
kHz
Power Amplifier Output (Pin 9)
Output Power 3) at 434 MHz transformed to 50 Ohm.
POUT, 434 POUT, 434 POUT, 434 5
dBm dBm dBm
VS = 2.1 V VS = 3.0 V VS = 4.0 V
Power Down Mode Control (Pin 10)
Power Down mode PLL Enable mode Transmit mode Input bias current PDWN
V PDWN V PDWN V PDWN IPDWN
0 1.5 1.5
0.5 VS VS 38
V V V A
VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = V S
1) a) b) c)
When the minimum TA is increased by tbd.C, the minimum fVCO decreases by 1 MHz. When the maximum TA is decreased by tbd.C, the maximum fVCO increases by 1 MHz. When the minimum VS is increased by tbd. mV, the maximum fVCO increases by 1 MHz. Restriction of c): The maximum fVCO must not be increased by more than tbd. MHz by increasing V S. All three measures can be taken independently and additive. 2) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA
3) Matching circuitry as used in the 50 Ohm-Output Testboard. Tolerances of the passive elements not taken into account. Range @ 2.1 V, +25C: dBm +/- dBm Typ. temperature dependency at 2.1 V: + dBm@-40C and - dBm@+125C, reference +25C Range @ 3.0 V, +25C: 5.0 dBm +/- dBm Typ. temperature dependency at 3.0 V: + dBm@-40C and - dBm@+125C, reference +25C Range @ 4.0 V, +25C: dBm +/- dBm Typ. temperature dependency at 4.0 V: + dBm@-40C and - dBm@+125C, reference +25C
Wireless Components
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Target Specification, July 2003

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